cystech electronics corp. spec. no. : c143l3 issued date : 2016.01.22 revised date : 2016.02.22 page no. : 1/9 mtb020n03kl3 cystek product specification 30v n-channel enhancement mode mosfet mtb020n03kl3 bv dss 30v i d @v gs =10v, t a =25 c 7.4a r dson @v gs =10v, i d =4a 21.4m (typ) r dson @v gs =4.5v, i d =3a 25.7m (typ) features ? single drive requirement ? low on-resistance ? fast switching characteristic ? esd protected gate ? pb-free lead plating package symbol outline sot-223 mtb020n03kl3 g d s d g gate s source d drain ordering information device package shipping MTB020N03KL3-0-T3-G sot-223 (pb-free lead plating and halogen-free package) 2500 pcs / tape & reel environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t3 :2500 pcs/tape & reel, 13? reel product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c143l3 issued date : 2016.01.22 revised date : 2016.02.22 page no. : 2/9 mtb020n03kl3 cystek product specification absolute maximum ratings (ta=25 c) parameter symbol limits unit drain-source voltage v ds 30 gate-source voltage v gs 20 v continuous drain current @v gs =10v, t a =25 c 7.4 continuous drain current @v gs =10v, t a =70 c i d 5.9 pulsed drain current *1 i dm 37 a t a =25 2.7 total power dissipation *2 t a =100 p d 1.1 w operating junction and storage temperature range tj, tstg -55~+150 c note : *1 . pulse width limited by safe operating area *2. surface mounted on a 1 in 2 pad of 2 oz. copper, t 10s. thermal data parameter symbol value unit thermal resistance, junction-to-case, max r jc 18 thermal resistance, junction-to-ambient, max r ja 45 (note) c/w note : surface mounted on a 1 in 2 pad of 2 oz. copper, t 10s; 120 c/w when mounted on minimum copper pad. electrical characteristics (tj=25 c, unless otherwise noted) symbol min. typ. max. unit test conditions static bv dss 30 - - v v gs =0v, i d =250 a ? bv dss / ? tj - 0.02 - v/ c reference to 25 c, i d =250 a v gs(th) 1.0 - 2.5 v v ds =v gs , i d =250 a i gss - - 10 v gs = 16v, v ds =0v - - 1 v ds =30v, v gs =0v i dss - - 25 a v ds =24v, v gs =0v (tj=70 c) - 21.4 27 i d =4a, v gs =10v *r ds(on) - 25.7 35 m i d =3a, v gs =4.5v *g fs - 4.5 - s v ds =10v, i d =4a dynamic ciss - 450 - coss - 79 - crss - 60 - pf v ds =15v, v gs =0, f=1mhz *t d(on) - 5.8 - *t r - 18.6 - *t d(off) - 33.8 - *t f - 11.8 - ns v ds =15v, i d =1a, v gs =10v, r g =6
cystech electronics corp. spec. no. : c143l3 issued date : 2016.01.22 revised date : 2016.02.22 page no. : 3/9 mtb020n03kl3 cystek product specification *qg - 12.3 - *qgs - 1.3 - *qgd - 4.2 - nc v ds =24v, i d =4a, v gs =5v source-drain diode *v sd - 0.81 1.2 v v gs =0v, i s =2a *i s - - 2.3 *i sm - - 9.2 a trr - 9.7 - ns qrr - 3.7 - nc v gs =0v, i f =2.3a, di f /dt=100a/ s *pulse test : pulse width 300 s, duty cycle 2% recommended soldering footprint
cystech electronics corp. spec. no. : c143l3 issued date : 2016.01.22 revised date : 2016.02.22 page no. : 4/9 mtb020n03kl3 cystek product specification typical characteristics typical output characteristics 0 5 10 15 20 25 30 35 40 01234 5 brekdown voltage vs junction temperature 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage 10v,9v,8v,7v,6v,5v vds, drain-source voltage(v) i d , drain current (a) 4.5v 4v 3.5 v i d =250 a, v =0v v gs =3v gs static drain-source on-state resistance vs drain current 10 100 0.01 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =10v v gs =4.5v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 048121620 i dr , reverse drain current(a) v sd , source-drain voltage(v) static drain-source on-state resistance vs gate-source voltage 0 30 60 90 120 150 024681 v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) tj=25c v gs =0v tj=150c 0 i d =4a drain-source on-state resistance vs junction tempearture 0 0.4 0.8 1.2 1.6 2 2.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =10v, i d =4a r ds( on) @tj=25c : 21.4m typ. v gs =4.5v, i d =3a r ds( on) @tj=25c : 25.7mtyp.
cystech electronics corp. spec. no. : c143l3 issued date : 2016.01.22 revised date : 2016.02.22 page no. : 5/9 mtb020n03kl3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 10 100 1000 0 5 10 15 20 25 30 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) v gs(th) , normalized threshold voltage i d =250 a i d =1ma forward transfer admittance vs drain current 0.01 0.1 1 10 0.001 0.01 0.1 1 10 i d , drain current(a) g fs , forward transfer admittance(s) ta=25c pulsed v ds =10 v v ds =15v gate charge characteristics 0 2 4 6 8 10 02468101214 qg, total gate charge(nc) v gs , gate-source voltage(v) i d =4a v ds =24v v ds =15v maximum safe operating area 0.01 0.1 1 10 100 0.1 1 10 100 v ds , drain-source voltage(v) i d , drain current(a) t a =25c, tj=150c v gs =10v, r ja =45c/w single pulse dc 100ms r dson limited 100 s 1ms 10 s 10ms maximum drain current vs junction temperature 0 1 2 3 4 5 6 7 8 9 25 50 75 100 125 150 175 tj, junction temperature(c) i d , maximum drain current(a) t a =25c, v gs =10v, r ja =45c/w
cystech electronics corp. spec. no. : c143l3 issued date : 2016.01.22 revised date : 2016.02.22 page no. : 6/9 mtb020n03kl3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 5 10 15 20 25 30 35 40 012345 v gs , gate-source voltage(v) i d , drain current(a) v ds =10v single pulse power rating, junction to ambient (note on page 2) 0 10 20 30 40 50 0.0001 0.001 0.01 0.1 1 10 100 pulse width(s) power (w) t j(max) =150c t a =25c r ja =45c/w transient thermal response curves 0.01 0.1 1 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *r ja (t) 4.r ja =45c/w
cystech electronics corp. spec. no. : c143l3 issued date : 2016.01.22 revised date : 2016.02.22 page no. : 7/9 mtb020n03kl3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c143l3 issued date : 2016.01.22 revised date : 2016.02.22 page no. : 8/9 mtb020n03kl3 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. spec. no. : c143l3 issued date : 2016.01.22 revised date : 2016.02.22 page no. : 9/9 mtb020n03kl3 cystek product specification sot-223 dimension *: typical inches millimeters inches millimeters dim min. max. min. max. 321 f b a c d e g h a1 a2 i style: pin 1.gate 2.drain 3.source marking: 3-lead sot-223 plastic surface mounted package cystek package code: l3 device name date code tyn3 dim min. max. min. max. a 0.1142 0.1220 2.90 3.10 g 0.0551 0.0709 1.40 1.80 b 0.2638 0.2874 6.70 7.30 h 0.0098 0.0138 0.25 0.35 c 0.1299 0.1457 3.30 3.70 i 0.0008 0.0039 0.02 0.10 d 0.0236 0.0315 0.60 0.80 a1 *13 o - *13 o - e *0.0906 - *2.30 - a2 0 o 10 o 0 o 10 o f 0.2480 0.2638 6.30 6.70 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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